This invention relates generally to digital integrated circuits and more particularly to digital integrated circuits including level-sensitive scan design (LSSD) storage elements, muxed-flop design storage elements, or clocked LSSD design storage elements, in which the storage elements have both a functional and a shift mode of operation.
Digital integrated circuits often include a great number of storage elements, such as latches or flip-flops, which temporarily store logical states within the integrated circuit. There are several situations in which it is useful to be able to set the states of such latches and flip-flops. For example, if it is desired to operate an integrated circuit from a known initial state, it is often necessary to be able to input states into the various latches and flip-flops of the integrated circuit from an external data pin. Also, it is useful to be able to test such an integrated circuit by shifting a test vector comprised of a sequence of "bits" through a chain of latches and/or flip-flops to ensure that the integrated circuit is functioning properly. In view of the foregoing, various specialized storage elements (latches and/or flip-flops) were developed which have two modes of operation. In a first mode of operation, the storage elements are set in a "functional" mode such that the integrated circuit performs its normal operational tasks. In a second or "shift" mode, data is sequentially shifted through the storage elements and out an output pin of the integrated circuit for diagnostic analysis.
In FIG. 1, a simplified schematic of an integrated circuit I is shown to include three modules, M1, M2, and M3. Digital integrated circuits are often designed in modular form, wherein each module performs a particular, global function, such as memory, logic, input/output, etc. Each of the modules M1, M2, and M3, can include storage elements E. As explained previously, these storage elements can comprise latches (which are level-sensitive devices) or flip-flops (which are edge-triggered devices), as is well known to those skilled in the art. Each of these storage elements E can hold a "state", i.e., can be a logical high ("HI"), or a logical low ("LO").
With continuing reference to FIG. 1, module M1 can be electrically coupled to a pair of input pins, here labeled "Shift In #1," and "CLK #1." Data applied to the "Shift In #1" pin is shifted into the series of storage elements E with each clock pulse on pin "CLK #1 ." In this way, the states of the storage elements E in module M1 can be set to a known state. Likewise, the storage elements E of module M2 can be set to a known state by placing data on pin "Shift In #2" and applying clock pulses to pin "CLK #2." If module M2 includes "n" storage elements E, after n+1 clock pulses on input pin "CLK 2" data from "Shift In #2" will start shifting out on pin "Shift Out #2."
The situation gets more complicated with respect to module M3. The module M3 also includes a number of storage elements E, but the data entering module M3 is developed by internal logic of module M1. Also, the clock for the storage elements E in module M3 is generated by the logic of module M1. In this instance, the prior art has been unable to scan-in data to an internal or "buried" module M3 so as to reliably set the states of the storage elements E.
The block diagram of FIG. 1 illustrates the storage elements E when they are in the second, or "shift" mode. The interconnections of the storage elements E with each other and with other circuit elements when in the functional mode are not illustrated in FIG. 1. The prior art provides well known methods and circuitry (not shown) for switching the storage elements E between the shift mode and the normal, functional mode.
The prior art discloses three basic ways of creating storage elements with the aforementioned two modes of operation. A first prior art method is known as level-sensitive scan design (LSSD) where, in the functional mode, the storage element is a level-sensitive latch controlled by the system clock and, when in the shift mode, the storage element is a latch sensitive to two non-overlapping level-sensitive clocks. Since it is a level-sensitive design, LSSD methodology is not very sensitive to clock skew. However, the problem with LSSD is that it is level rather than edge triggered in the functional mode, which requires significantly different clock distribution techniques from edge triggered design, and entails more design methodology restrictions.
A second methodology is known as the "muxed flop" (i.e. multiplexed flip-flop) design. Muxed flop design is currently the most popular methodology for creating storage elements for integrated circuits having two modes of operation. However, muxed flop design has a moderate area penalty and also has a moderate speed penalty over LSSD. It is furthermore quite sensitive to clock skew in the shift mode.
A design implementation which is a hybrid between LSSD design and muxed flop design is known as "clocked LSSD." Like the LSSD design, it is not sensitive to scan clock skew. Existing implementations of clocked LSSD circuits have a heavy area penalty but no speed penalty over the LSSD method. As will be discussed in greater detail subsequently, the heavy area penalty exists because at least three latches are used to construct the storage elements.
In FIG. 2a, a typical prior art LSSD storage element includes a master latch and a slave latch. When in the shift mode, two clocks (which are separate from the system clock) operate in conjunction to transfer data from the master latch to the slave latch, and the scan output (SO) is developed at the Q output of the slave latch. As noted in FIG. 2a, the master and slave latches are level sensitive. A flip-flop design is similar, except the master and slave latches are both operated from the same clock, which is a merger of the two clocks of the LSSD storage element, which controls both the functional and the shift modes.
In FIG. 2b, a clocked LSSD storage element of the prior art includes three latches, wherein data is latched into the first latch at a SI input and is transferred out of a third latch at a SO output. A second latch provides a Q output when in the functional mode.
An example of the type of storage element illustrated in FIG. 2b can be found in U.S. Pat. No. 4,553,236 of Zasio (hereinafter referred to as Zasio '236). In Zasio '236, a scannable latch circuit is provided with dual isolated outputs, one of which is used as a latch output and the other of which is used as a shift register output. A computer system, in which the scannable logic is used in conjunction with combinatorial logic and error detection circuitry, may monitor the latch output for error detection and other purposes without having to slow down the system operating speed.
While Zasio '236 performs admirably, it does suffer from several drawbacks. For one, Zasio '236 pays a heavy area penalty for providing clocked LSSD functionality because it requires three latches and supporting circuitry. Secondly, since data is shifted into the latches of Zasio '236 by a edge-triggered clock, the Zasio '236 storage elements are quite vulnerable to skew when capturing data in a functional mode. Furthermore, Zasio '236 cannot deal with internal clocks, such as the internal clock of module M3 of FIG. 1.
Digital integrated circuits employing one of the aforementioned forms of dual-mode storage element technology employ Automated Test Pattern Generation ("ATPG") algorithms and software to run tests on the integrated circuit such as the "D" algorithm, "Podem", and other tests well known to those skilled in the art. It would therefore be desirable that any improved storage element technology for digital integrated circuits would be compatible with such existing ATPG algorithms and software, or at least would be able to use such ATPG algorithms and software with minimal amounts of modification.